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Artedas Europe

EMA TimingDesigner

Timing diagram editor enables rapid specification of design requirements

TimingDesigner is the interactive timing analysis tool designers trust to deliver fast and accurate results for timing critical designs such as high-speed, multi-frequency designs.

TimingDesigner uses an intuitive timing diagram approach for developing specifications to drive the design process, analyzing timing to answer critical design questions, and documenting results to clearly illustrate and communicate the design implementation. TimingDesigner is ideal for high-speed, multi-frequency designs. In these designs it is essential to accurately model and analyze signal relationships between devices on a board or between embedded functions on an ASIC or programmable IC. TimingDesigner can evaluate comprehensive sets of timing alternatives and provide direction to the most complex of timing challenges, enabling designers to manage and monitor timing margins through the design process.

 

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EMA TimingDesigner Datasheet

EMA Automation

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Avantages de TimingDesigner

  • Le diagramme temporel convivial fournit rapidement une estimation des caractéristiques du système
  • Logiciel lié dynamiquement à un tableur temporel afin de modéliser précisément les effets des contraintes et des délais
  • Ce logiciel très puissant d’analyse temporelle identifie rapidement les marges temporelles les plus critiques
  • Les mises à jour instantanées des diagrammes temporels effectuent des évaluations rapides de différents scénarii
  • Gestionnaire de projet fiable
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Quickly Evaluate Alternatives

Evaluating alternatives is key to developing specifications that can accurately convey design details and timing budgets.
TimingDesigner contains an easy-to-use timing diagram editor that enables rapid specification of design requirements including: timing constraints, cause-and-effect relationships, delays, and sequence protocols. TimingDesigner supports the early investigation of timing options and provides a straightforward means to clearly specify the sequence of events and timing relationships required for modules or subsystems to communicate as expected.

Analyze Interfaces

Interfaces between embedded processors, memory, and logic functions on a chip or between devices on a circuit board are often the source of difficult-to-locate timing violations, especially for high-speed designs. TimingDesigner's robust timing engine uses a timing diagram specification to accurately analyze parameters and identify violations that may otherwise go undetected until late in the design process. The ability to quickly evaluate design alternatives and compute worst-case timing margins makes TimingDesigner an excellent choice to help develop solutions for specific problem areas.
 

Documentation

TimingDesigner delivers the ability to clearly and accurately communicate design details by exporting or linking timing diagram files generated during the design process through OLE support or in its native format. The standard, easy-to-interpret format of timing diagram specifications improves the communication of complex design information. In addition robust project manager organizes component diagrams within a single project tree and eases the management and exchange of timing data among project team members.

Advanced Delay Path Analysis

TimingDesigner traces all delay paths specified in the timing diagram, removes common uncertainties, adjusts for track delays, selects critical paths and then computes worst-case timing margins. The effects of complex design changes can be instantly visualized. Automatically calculated timing constraints identify timing violations in easy-to-distinguish red, as well as in a convenient Violations Report window, so problem areas can be addressed quickly. A configurable format to generate reports and export timing constraint information is available using the Dynamic Text window.

EMA Automation