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Artedas Europe

Allegro FPGA System Planner

Scalable, cost-effective FPGA-PCB co-design solution

Integrating large-pin-count FPGAs with many different types of user-configurable pins and assignment rules extends the time to do pin assignment. Manual pin assignment approaches can extend design cycles and increase the risk of unnecessary PCB re-spins. Cadence replaces manual and error-prone processes with two placement-aware technologies that automate pin assignment.
Allegro FPGA System Planner provides FPGA-PCB co-design that allows users to create optimum, correct-by-construction pin assignments in a complete, scalable solution.

The Allegro FPGA System Planner offers a complete, scalable technology for FPGA-PCB co-design that allows users to automatically create an optimum placement-aware initial pin assignment for one or more FPGAs. It also allows users to optimize pin assignment after placement or during routing of signals on the PCB.

 

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Allegro FPGA System Planner Datasheet

Cadence

Allegro Design Authoring

 

Cadence Allegro Design Authoring provides the first step in PCB design definition, with productivity enhancing features and constraint management to keep your design flow on track.

Allegro PCB Designer

 

Allegro PCB Designer quickly takes simple or complex designs from concept to production in a constraint-driven design PCB Design Environment that helps overcome today's design challenges.

 

Allegro PSpice Simulator

 

Allegro PSpice Simulator provides complete pre- and post-layout testing for analog and mixed-signal designs with powerful simulation, debugging, design, and analysis utilities.

 

Allegro FPGA System Planner benefits

  • Scalable FPGA-PCB co-design solution from OrCAD Capture to Allegro GXL
  • Shortens time for optimum initial pin assignment, accelerating PCB design schedules
  • Accelerates integration of FPGAs with Cadence PCB design creation environments
  • Eliminates unnecessary, frustrating design iterations during the PCB layout process
  • Eliminates unnecessary physical prototype iterations due to FPGA pin assignment errors
  • Reduces PCB layer count through placement-aware pin assignment and optimization
  • Enables interface-based connectivity definition for the FPGA system
  • Enables placement-aware pin assignment synthesis that is FPGA-DRC accurate
  • Allows architectural exploration for FPGA system
  • Speeds ASIC prototyping using FPGAs
   Complementary tools for Allegro Design Entry CIS

EMA CIP  >
EMA TmingDesigner

Allegro PSpice Simulator >

Allegro PCB Designer  >
Allegro Sigrity  >

Extensive Scalability

Scalability is a key component of Allegro FPGA System Planners; it allows designers to pay for just the level of capabilities they need.

Specify Connectivity

The Allegro FPGA System Planner allows users to specify connectivity between components within the FPGA sub-system at a higher level through interface definitions.
Users can create interfaces such as DDR2, DDR3, and PCI Express, and use these to specify connectivity between an FPGA and a memory DIMM module or between two FPGAs. TAllegro FPGA System Planner understands differential signals, and power signals, as well as clock signals.
Allegro FPGA System Planner comes with an FPGA device library to help with selection of devices to be placed. It uses Allegro PCB Editor footprints for the floorplan view and allows users to quickly create relative placement of the FPGA system components.

Creation of System Placement and Floorplan Views

FPGA System Placement Views can be created using Allegro PCB Editor footprints.
Users specify connectivity between components at a high level using interfaces (ex. DDRx, PCI Express, SATA, Front Side Bus, etc.) that connect FPGAs and other components in the design. This shortens the time to specify design intent for the FPGA system. Once the connectivity of the FPGA to other components in the sub-system is defined, the product synthesizes the pin assignment based on the user's design intent, available FPGA resources, component placement around the FPGA, and the FPGA vendor's pin assignment rules.
The floorplan view uses existing footprint libraries from Allegro PCB Editor. Should placement change during layout, pin optimization using FPGA System Planner can be accessed directly from Allegro PCB Editor and updated.

Allegro flagship products

Allegro Design entry CIS

Integrates OrCAD Capture schematic design application with the features of a component information system

Allegro Design Authoring

Advanced, scalable schematic entry with powerful features including reuse of designs

Allegro PCB Designer

Quickly takes simple or complex designs from concept to production in a constraint-driven design

Allegro PSpice Simulator

A complete for analog and mixed-signal designs with powerful simulation, debugging, design, & analysis utilities

Allegro FPGA System Planner

Provides FPGA-PCB co-design that allows users to create optimum, correct-by-construction pin assignments

Allegro Sigrity

System-level signal integrity & Analysis anabling a streamlined, predictable path from implementation to verification